1. Field of the Invention
The present invention relates generally to delay locked loop (DLL) circuits useful for use in semiconductor integrated devices and particularly to DLL circuits capable of adjusting a clock""s phase with high precision.
2. Description of the Related Art
A conventional DLL circuit employs a delay chain such as an inverter chain to provide phase matching. The phase matching is provided by automatically selecting from the delay chain""s amount of delay varying by a fixed value an amount of delay as required, and holding the amount of delay selected. To provide phase matching with higher precision than the fixed value, as shown in FIG. 14, between inverters 60 and 70 capacitors 62, 64, 66 having different levels of capacitance are connected via N-channel MOS transistors 61, 63, 65 and addresses a0, a1, a2 are applied to selectively turn on/off N-channel MOS transistors 61, 63, 65. Thus, two inverters 60 and 70 provide an amount of delay in a fixed range for adjusting a clock""s phase.
In the conventional DLL circuit, however, the inverter chain provides a fixed amount of delay and the capacitors provide a delay smaller than the fixed amount of delay and the inverter chain and the capacitors employ different delay systems. As such, voltage, process and temperature affect the inverter chain and the capacitor differently and the clock""s phase can hardly be adjusted.
The FIG. 14 capacitors 62, 64, 66 capacitance variation disadvantageously results in capacitors 62, 64, 66 having an amount of delay exceeding an amount of delay provided by inverters 60 and 70, so that the clock""s phase cannot be adjusted in the range of the amount of delay of inverters 60 and 70 with high precision.
The present invention contemplates a DLL circuit impervious to voltage, process, temperature and the like and thus capable of adjusting a phase of a clock with high precision.
In accordance with the present invention the DLL circuit includes a phase comparator, a counter, a first delay circuit and a second delay circuit. The phase comparator compares a phase of a delay clock with a phase of a reference clock. The counter refers to a result received from the phase comparator, to provide a counting up/down operation and output first and second addresses. The first delay circuit in response to the reference clock generates first and second signals having therebetween a phase difference of a fixed amount and responds to the generated first and second signals and refers to the first signal to generate a fine adjustment clock existing between a phase of the first signal and a phase of the second signal. The second delay circuit refers to the second address to delay the fine adjustment clock by the fixed amount multiplied by an integer to output a delay clock.
In the present DLL circuit, a result of comparing a phase of a delay clock with that of a reference clock can be referred to to provide a counting up/down operation to generate first and second addresses. The first address can be referred to to provide fine control to control the reference clock""s phase in the range of a fixed amount T and the second address can be referred to provide coarse control to control the reference clock""s phase with the precision of the fixed amount T. Thus the delay clock""s phase can be matched to the reference clock""s phase in the order smaller than the fixed amount T with high precision.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.